參數(shù)資料
型號： EVAL-ADF4158EB1Z
廠商： Analog Devices Inc
文件頁數(shù)： 15/36頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADF4158
標準包裝： 1
主要目的： 計時，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4158
主要屬性： 單路分數(shù)-N PLL
已供物品： 板
ADF4158
Data Sheet
Rev. G | Page 22 of 36
DEVIATION REGISTER (R5) MAP
With Register R5 DB[2:0] set to [1, 0, 1], the on-chip deviation
register is programmed as shown in Figure 28.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Tx Ramp CLK
Setting DB29 to 0 uses the clock divider clock for clocking the
ramp. Setting DB29 to 1 uses the Tx data clock for clocking
the ramp.
PAR Ramp
Setting DB28 to 1 enables the parabolic ramp. Setting DB28 to 0
disables the parabolic ramp.
Interrupt
DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FARC value of a ramp
at a given moment in time (rising edge on the TXDATA pin triggers
the interrupt). From these bits, frequency can be obtained. After
readback, the sweep might continue or stop at the readback
frequency.
FSK Ramp Enable
Setting DB25 to 1 enables the FSK ramp. Setting DB25 to 0 disables
the FSK ramp.
Ramp 2 Enable
Setting DB24 to 1 enables the second ramp. Setting DB24 to 0
disables the second ramp.
Deviation Select
Setting DB23 to 0 chooses the first deviation word. Setting DB23 to
1 chooses the second deviation word.
4-Bit Deviation Offset Word
DB[22:19] determine the deviation offset. The deviation offset
affects the deviation resolution.
16-Bit Deviation Word
DB[18:3] determine the signed deviation word. The deviation word
defines the deviation step.
DB31
16-BIT DEVIATION WORD
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
TR1
PR1
I2
I1
FRE1 R2E1 DS1
DO4 DO3 DO2 DO1
D16
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
C3(1) C2(0) C1(1)
0
782
8-
1
16
I2
I1
INTERRUPT
0
INTERRUPT OFF
11
LOAD CHANNEL CONTINUE SWEEP
D16
D14
.......... D2
D1
16-BIT DEVIATION WORD
0
..........
0
..........
0
1
0
..........
1
0
2
0
..........
1
3
1
..........
1
–1
1
..........
1
0
–2
1
..........
0
1
–3
1
0
..........
0
–32,768
D4
D3
D1
D2
4-BIT DEV OFFSET
WORD
D
EV
SE
L
RAM
P
2
E
N
F
S
K
RA
M
P
E
N
INT
E
RRUP
T
P
AR
RAM
P
PR1
PAR RAMP
0DISABLED
1
ENABLED
0
1
0
1
NOT USED
LOAD CHANNEL STOP SWEEP
FRE1 FSK RAMP ENABLE
0DISABLED
1
ENABLED
R2E1
RAMP 2 ENABLE
0DISABLED
1
ENABLED
DO4
DO3
DO2
DO1
4-BIT DEV OFFSET WORD
0000
0
0001
1
0010
2
0011
3
...
.
...
.
...
.
1001
9
DS1
DEV SEL
0
DEV WORD 1
1
DEV WORD 2
R
ESER
VED
T
X
RAM
P
CL
K
TR1 TX RAMP CLK
0CLK DIV
1TX DATA
0
1
..........
1
32,767
.
..........
.
..........
.
Figure 28. Deviation Register (R5) Map
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