參數(shù)資料
型號： EVAL-AD7686CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/28頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD7686
標準包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF
在以下條件下的電源（標準）： 15mW @ 500kSPS，5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7686
已供物品： 板
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AD7686
Rev. B | Page 19 of 28
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is generally used when multiple AD7686s are
connected to an SPI-compatible digital host. A connection
diagram example using two AD7686 devices is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers.
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7686 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th
SCK falling edge or when SDI goes high, whichever occurs first,
SDO returns to high impedance and another AD7686 can
be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
02
96
9-
0
3
8
CNV
SCK
SDO
SDI
AD7686
CNV
SCK
SDO
SDI
AD7686
Figure 37. CS Mode 4-Wire, No Busy Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
tDIS
SCK
12
3
30
31
32
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14
15
tSCK
tSCKL
tSCKH
D0
D15
D14
17
18
16
SDI(CS2)
02
96
9-
0
39
Figure 38. CS Mode 4-Wire, No Busy Indicator Serial Interface Timing
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