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參數(shù)資料
| 型號： | EVAL-AD7665EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD76XXEDZ |
| 標準包裝： | 1 |
| 系列： | * |
REV.
AD7665
–17–
DIGITAL INTERFACE
The AD7665 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7665 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7665
to the host system interface digital supply. Finally, by using the
OB/
2C input pin, twos complement and straight binary coding
can be used.
The two signals
CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually,
CS allows the selection of each AD7665 in
multicircuit applications and is held LOW in a single AD7665
design.
RD is generally used to enable the conversion result on
the data bus.
t1
t3
t4
t11
CNVST
BUSY
DATA BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7665 is configured to use the parallel interface when the
SER/
PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or during
the following conversion as shown in Figures 14 and 15, respec-
tively. When the data is read during the conversion, however,
it is recommended that it be read-only during the first half of the
conversion phase. That avoids any potential feedthrough between
voltage transients on the digital interface and the most critical
analog conversion circuitry.
RD
BUSY
CS
CURRENT
CONVERSION
DATA BUS
t12
t13
Figure 14. Slave Parallel Data Timing for Reading (Read
after Convert)
t1
CS = 0
CNVST,
RD
PREVIOUS
CONVERSION
t3
t12
t13
t4
BUSY
DATA BUS
Figure 15. Slave Parallel Data Timing for Reading (Read
during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB are swapped and the
LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16 data bits
can be read in two bytes on either D[15:8] or D[7:0].
CS
BYTE
PINS D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t
12
t
12
t
13
RD
PINS D[7:0]
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7665 is configured to use the serial interface when the
SER/
PAR is held HIGH. The AD7665 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7665 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held LOW. It also gener-
ates a SYNC signal to indicate to the host when the serial data is
valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on RDC/SDIN input, the data can be
read after each conversion or during conversion. Figures 17
and 18 show the detailed timing diagrams of these two modes.
Usually, because the AD7665 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
Serial Mode when it can be used.
C
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