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參數(shù)資料
| 型號： | EVAL-AD7665EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD76XXEDZ |
| 標準包裝： | 1 |
| 系列： | * |
REV.
AD7665
–19–
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
t34
X15
X14
X
12
3
14
15
16
17
18
EXT/
INT = 1
RD = 0
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7665 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS and the data are
output when both
CS and RD are LOW. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either normally
HIGH or normally LOW when inactive. Figures 19 and 21 show
the detailed timing diagrams of these methods.
While the AD7665 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7665 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that
when an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that does not transition during the latter half of BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both
CS
and
RD are LOW. The data is shifted out, MSB first, with
16 clock pulses and is valid on both the rising and falling edge
of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7665 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 20. Simultaneous sampling is possible by using a com-
mon
CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used
to shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
DATA
OUT
AD7665
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7665
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7665s in a Daisy-Chain Configuration
C
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| EVAL-AD7667CB | 制造商:Analog Devices 功能描述: |
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