t12 t13 02964-0-" />
參數(shù)資料
型號: EVAL-AD7652CBZ
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7652
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: 0 ~ 2.5 V
在以下條件下的電源(標(biāo)準(zhǔn)): 65mW @ 500kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7652
已供物品:
相關(guān)產(chǎn)品: AD7652ASTZ-ND - IC ADC 16BIT 500KSPS REF 48LQFP
AD7652ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP
AD7652
CURRENT
CONVERSION
BUSY
DATA
BUS
t12
t13
02964-0-013
RD
CS
DIGITAL INTERFACE
The AD7652 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7652 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7652 to the host system interface digital supply. Finally, by
using the OB/2C input pin, both twos complement or straight
binary coding can be used.
The two signals, CS and RD, control the interface. CS and RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually CS allows the selection
of each AD7652 in multicircuit applications and is held LOW in
a single AD7652 design. RD is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7652 is configured to use the parallel interface when
SER/PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F
, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
Figure 29. Slave Parallel Data Timing for Reading (Read after Convert)
Figure 30. Slave Parallel Data Timing for Reading (Read during Convert)
PREVIOUS
CONVERSION
t1
t3
t12
t13
t4
BUSY
DATA
BUS
02964-0-014
CNVST,
RD
CS = 0
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in
, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
Figure 31. 8-Bit Parallel Interface
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t12
t13
02965-0-025
SERIAL INTERFACE
The AD7652 is configured to use the serial interface when
SER/PAR is held HIGH. The AD7652 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
Rev. 0 | Page 20 of 28
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