VDD = 2.35 V to 5.2" />
參數(shù)資料
型號： EVAL-AD7476ACBZ
廠商： Analog Devices Inc
文件頁數(shù)： 29/29頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7476A
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 5.25 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 17.5mW @ 1MSPS，5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7476A
已供物品： 板，CD
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AD7476ARTZ-REEL7-ND - IC ADC 12BIT 1MSPS LP SOT23-6
AD7476ABKSZ-500RL7-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AAKSZ-REEL7-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AAKSZ-500RL7TR-ND - IC ADC 12BIT 1MSPS LP SC70-6
AD7476AYRMZ-REEL7-ND - IC ADC 12BIT 1MSPS LP 8MSOP
AD7476AAKSZ-REEL-ND - IC ADC 12BIT 1MSPS LP SC70-6
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更多...
AD7476A/AD7477A/AD7478A
Rev. F | Page 8 of 28
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK2
10
kHz min3
A, B grades
20
kHz min3
Y grade
20
MHz max
tCONVERT
16 × tSCLK
AD7476A
14 × tSCLK
AD7477A
12 × tSCLK
AD7478A
tQUIET
50
ns min
Minimum quiet time required between bus relinquish
and start of next conversion
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS to SCLK setup time
22
ns max
Delay from CS until SDATA three-state disabled
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
SCLK to data valid hold time
10
ns min
VDD ≤ 3.3 V
9.5
ns min
3.3 V < VDD ≤ 3.6 V
7
ns min
VDD > 3.6 V
36
ns max
SCLK falling edge to SDATA high impedance
t7 values also apply to t8 minimum values
ns min
SCLK falling edge to SDATA high impedance
tPOWER-UP7
1
μs max
Power-up time from full power-down
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum fSCLK at which specifications are guaranteed.
4
Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V, and
0.8 V or 2.0 V for VDD > 2.35 V.
5
Measured with a 50 pF load capacitor.
6
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD7476CB 制造商:Analog Devices 功能描述:Evaluation Board For AD7476 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD7476CBZ 功能描述:BOARD EVAL FOR AD7476 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
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EVAL-AD7477ACB4 制造商:AD 制造商全稱:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70
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