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參數(shù)資料
型號(hào)： EVAL-AD7329CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/41頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7329CBZ
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 30mW @ 1MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7329
已供物品： 板
相關(guān)產(chǎn)品： AD7329BRUZ-REEL7-ND - IC ADC 12BIT+SAR 8CHAN 24-TSSOP
AD7329BRUZ-REEL-ND - IC ADC 12BIT+SAR 8CHAN 24-TSSOP
AD7329BRUZ-ND - IC ADC 12BIT 8CH MUX SPI 24TSSOP
Data Sheet
AD7329
Rev. B | Page 33 of 40
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
When the autoshutdown mode is selected, the AD7329
automatically enters shutdown on the 15th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down.
The AD7329 retains information in the registers during
autoshutdown. The track-and-hold section is in hold mode
during autoshutdown. On the rising CS edge, the track-and-
hold section, which was in hold during shutdown, returns to
track as the AD7329 begins to power up. The time to power up
from autoshutdown is 500 s.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 54 shows the part entering autoshutdown mode. The
AD7329 automatically begins to power up on the CS rising
edge. The tPOWER-UP is required before a valid conversion, initiated
by bringing the CS signal low, can take place. After this valid
conversion is complete, the AD7329 powers down again on the
15th SCLK rising edge. The CS signal must remain low again to
keep the part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7329 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown but allows the AD7329 to power up much faster,
which allows faster throughput rates.
As is the case with autoshutdown mode, the AD7329 enters
standby on the 15th SCLK rising edge when the control register
is updated (see Figure 54). The part retains information in the
registers during standby. The AD7329 remains in standby until
it receives a CS rising edge. The ADC begins to power up on the
CS rising edge. On the CS rising edge, the track-and-hold,
which was in hold mode while the part was in standby, returns
to track.
The power-up time from standby is 750 ns. The user should
ensure that 750 ns have elapsed before bringing CS low to
attempt a valid conversion. After this valid conversion is
complete, the AD7329 again returns to standby on the 15th
SCLK rising edge. The CS signal must remain low to keep the
part in standby mode.
Figure 54 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 54, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
CS
1
16
15
1
16
15
SCLK
SDATA
DIN
VALID DATA
DATA INTO CONTROL REGISTER
tPOWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS
PM1 = 1, PM0 = 0
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
IF PM1 = 1, PM0 = 0
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
05402-
049
Figure 54. Entering Autoshutdown/Autostandby Mode
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