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參數(shù)資料
| 型號： | EVAL-AD7329CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7329CBZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | iCMOS® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 30mW @ 1MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7329 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7329BRUZ-REEL7-ND - IC ADC 12BIT+SAR 8CHAN 24-TSSOP AD7329BRUZ-REEL-ND - IC ADC 12BIT+SAR 8CHAN 24-TSSOP AD7329BRUZ-ND - IC ADC 12BIT 8CH MUX SPI 24TSSOP |
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AD7329
Data Sheet
Rev. B | Page 20 of 40
TYPICAL CONNECTION DIAGRAM
Figure 34 shows a typical connection diagram for the AD7329.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7329 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7329 can operate
with either an internal or external reference. In Figure 34, the
AD7329 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The VCC pin can be connected to either a 3 V or a 5 V supply
voltage. The VDD and VSS are the dual supplies for the high
voltage analog input structures. The voltage on these pins must
be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6 for more
information). The VDRIVE pin is connected to the supply voltage
of the microprocessor. The voltage applied to the VDRIVE input
controls the voltage of the serial interface.
AD7329
VCC
VDD1
SERIAL
INTERFACE
FILTERING/BUFFERING
C/P
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
REFIN/REFOUT
CS
DOUT
VDRIVE
SCLK
DIN
DGND
10F
0.1F
+
MUXOUT+
ADCIN+
MUXOUT–
ADCIN–
10F
0.1F
+
10F
0.1F
+
ANALOG INPUTS:
±10V, ±5V, ±2.5V,
0V TO +10V
+15V
–15V
680nF
VSS1
VCC +2.7V TO +5.25V
1MINIMUM VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
05402-
031
10F
0.1F
+
+3V SUPPLY
Figure 34. Typical Connection Diagram, Single-Ended Mode
AD7329
VCC
VDD1
SERIAL
INTERFACE
FILTERING/BUFFERING
C/P
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
REFIN/REFOUT
CS
DOUT
VDRIVE
SCLK
DIN
DGND
10F
0.1F
+
M
UX
O
UT
–
M
UX
O
UT
+
ADC
IN
–
ADC
IN
+
10F
0.1F
+
10F
0.1F
ANALOG INPUTS:
±10V, ±5V, ±2.5V,
0V TO +10V
+15V
–15V
680nF
VSS1
VCC +2.7V TO +5.25V
1MINIMUM VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
05402-
032
10F
0.1F
+
+3V SUPPLY
+
Figure 35. Typical Connection Diagram, Differential Mode
ANALOG INPUT
Single-Ended Inputs
The AD7329 has a total of eight analog inputs when operating
in single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
ended mode.
AD73291
VIN+
V+
V–
VDD
VSS
VCC
5V
AGND
1ADDITIONAL PINS OMITTED FOR CLARITY.
05402-
033
Figure 36. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7329 can have four true differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including better noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 37 defines the configuration of the true
differential analog inputs of the AD7329.
AD73291
VIN+
VIN–
1ADDITIONAL PINS OMITTED FOR CLARITY.
05402-
034
Figure 37. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN pins in
each differential pair (VIN+ VIN). VIN+ and VIN should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × VREF mode, the amplitude of the
differential signal is 20 V to +20 V p-p (2 × 4 × VREF),
regardless of the common mode.
The common mode is the average of the two signals
(VIN+ + VIN)/2
and is therefore the voltage on which the two input signals are
centered.
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