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參數資料
| 型號： | EVAL-AD7324CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 22/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7324CBZ |
| 標準包裝： | 1 |
| 系列： | iCMOS® |
| ADC 的數量： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 1M |
| 數據接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標準）： | 30mW @ 1MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7324 |
| 已供物品： | 板 |
| 相關產品： | AD7324BRUZ-REEL-ND - IC ADC 12BIT+SAR 4CHAN 16-TSSOP AD7324BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP AD7324BRUZ-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP |
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AD7324
Data Sheet
Rev. B | Page 28 of 36
MODES OF OPERATION
The AD7324 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7324 is controlled by the power manage-
ment bits, Bit PM1 and Bit PM0, in the control register as shown
in Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance,
with the AD7324 being fully powered up at all times. Figure 46
shows the general operation of the AD7324 in normal mode.
The conversion is initiated on the falling edge of CS, and the
track-and-hold enters hold mode as described in the Serial
Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write
bit is set. The register is selected by programming the register
select bits (see Figure 46).
1
16
LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +
CONVERSION RESULT
DATA INTO CONTROL/SEQUENCE/RANGE REGISTER
SCLK
CS
DOUT
DIN
04864-
035
Figure 46. Normal Mode
The AD7324 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7324 is powered
down. The part retains information in the registers during full
shutdown. The AD7324 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7324 enters full shut-
down mode on the 15th SCLK rising edge once the control register
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15th SCLK rising edge once the control register is
updated. Figure 47 shows how the AD7324 is configured to exit
full shutdown mode. To ensure the AD7324 is fully powered up,
tPOWER-UP for full shutdown mode should elapse before the next
CS falling edge
CS
1
16
1
16
SCLK
SDATA
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
tPOWER-UP
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
04864-
041
Figure 47. Exiting Full Shutdown Mode
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