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參數(shù)資料
| 型號： | EVAL-AD7265EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7265 A/D CONV |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 輸入范圍： | 0 ~ 5 V |
| 在以下條件下的電源（標準）： | 7mW @ 3V，17mW @ 5V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7265 |
| 已供物品： | 板 |
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AD7265
Rev. A | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04
67
4
-04
1
CS
SGL/DIFF
1
2
3
4
5
6
7
8
REF SELECT
AVDD
DCAPA
VA1
AGND
DGND
VA2
23
A2
22
21
RANGE
18
VB1
19
AGND
20
DCAPB
24
A1
17
VB2
PIN 1
9
V
A3
10
V
A4
11
V
A5
12
V
A6
13
V
B6
14
V
B5
15
V
B4
16
V
B3
32
DV
DD
31
V
DR
IV
E
30
D
OU
T
A
29
DG
ND
28
D
OU
T
B
27
SC
L
K
26 25
A0
AD7265
TOP VIEW
(Not to Scale)
04674-002
24
23
22
21
1
2
3
32
DV
DD
A0
CS
SC
LK
D
OUT
B
DGND
D
OUT
A
V
DRIV
E
20
19
18
17
VB2
VB1
AGND
DCAPB
RANGE
SGL/DIFF
A2
A1
9
10
11
12
13
V
B5
V
B4
V
B3
V
B6
V
A6
V
A5
V
A4
V
A3
14
15
16
4
5
6
7
8
VA2
VA1
AGND
DCAPA
AVDD
REF SELECT
DGND
31
30
29
28
27
26
25
AD7265
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 3. 32-Lead SU-32-2
Figure 2. 32-Lead CP-32-2
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 29
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
2
REF SELECT
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used
as the reference source for both ADC A and ADC B. In addition, Pin D
A and Pin D
CAP
B must be tied to
decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the
AD7265 through the D
A pin and/or the D
B pin.
CAP
3
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The
AV
and DV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
4, 20
D
A, D
B
CAP
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference
can be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
5, 6, 19
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect
to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
7 to 12
V to V
A1
A6
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
13 to 18
VB6 to VB1
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
21
RANGE
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog
input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic
high when CS goes low, the analog input range is 2 × V . See the Analog Input Selection section for details.
REF
22
SGL/DIFF
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A
logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
23 to 25
A2 to A0
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
26
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265
and framing the serial data transfer.
27
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This
clock is also used as the clock source for the conversion process.
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