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參數(shù)資料
| 型號： | EVAL-AD7265EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7265 A/D CONV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 輸入范圍： | 0 ~ 5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 7mW @ 3V，17mW @ 5V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7265 |
| 已供物品： | 板 |
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AD7265
Rev. A | Page 25 of 28
In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V
AD7265 TO DSP563xx
The connection diagram in Figure 46 shows how the AD7265
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each operates in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).
DRIVE
pin of the AD7265 takes the same supply
voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore the
DSP563xx, if necessary.
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.
SCLK
DSP563xx1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCK0
SC12
SRD1
SRD0
CS
DOUTA
DOUTB
VDRIVE
VDD
SC02
SCK1
04674-039
AD72651
To implement the power-down modes on the AD7265, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
Figure 46. Interfacing the AD7265 to the DSP563xx
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