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參數(shù)資料
| 型號： | EVAL-AD5501EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5501 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 16M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 設(shè)置時間： | 45µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5501 |
Data Sheet
AD5501
Rev. C | Page 15 of 20
SERIAL INTERFACE
The AD5501 has a serial interface (SYNC, SCLK, SDI, and
SDO), which is compatible with SPI standards, as well as with
most DSPs. The AD5501 allows writing of data, via the serial
interface, to the input and control registers. The DAC register is
not directly writeable or readable.
The input shift register is 16 bits wide (see Table 8). The 16-bit
word consists of one read/write (R/W) control bit, followed by
three address bits and 12 DAC data bits. Data is loaded MSB first.
WRITE MODE
To write to a register, the R/W bit should be 0. The three address
bits in the input register (see Table 9) then determine the register to
update. The address bits (A2 to A0) should be 001 to write to the
DAC input register or 111 to write to the control register. Data
is clocked into the selected register during the remaining 12 clocks
of the same frame. Figure 3 shows a timing diagram of a typical
AD5501 write sequence. The write sequence begins by bringing
the SYNC line low. Data on the SDI line is clocked into the 16-bit
shift register on the rising edge of SCLK. On the 16th falling
clock edge, the last data bit is clocked in and the programmed
function is executed (that is, a change in the selected DAC input
register or a change in the mode of operation). The AD5501 does
not require a continuous SCLK and dynamic power can be saved
by transmitting clock pulses during a serial write only. At this
stage, the SYNC line can be kept low or be brought high. In either
case, it must be brought high for a minimum of 20 ns before the
next write sequence for a falling edge of SYNC to initiate the next
write sequence. Operate all interface pins close to the supply
rails to minimize power consumption in the digital input buffers.
READ MODE
The AD5501 allows data readback via the serial interface from
the DAC input register and the control register. To read back a
register, it is first necessary to tell the AD5501 that a readback is
required. This is achieved by setting the R/W bit to 1. The three
address bits then determine the register from which data is to
be read back. Data from the selected register is clocked out of
the SDO pin on the next 12 clocks of the same frame.
The SDO pin is normally three-stated but becomes driven on the
rising edge of the fifth clock pulse. The pin remains driven until the
data from the register has been clocked out or the SYNC pin is
returned high. Figure 4 shows the timing requirements during a
read operation. Note that due to timing requirements of t14
(110 ns), the maximum speed of the SPI interface during a read
operation should not exceed 9 MHz.
WRITING TO THE CONTROL REGISTER
The control register is written when Bits[DB14:DB12] are 1. The
control register sets the power-up state of the DAC output. A
write to the control register must be followed by another write
operation. The second write operation can be a write to a DAC
input register or a NOP write. Figure 17 shows some typical
combinations.
Table 8. Input Register Bit Map
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
A2
A1
A0
Data
Table 9. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register.
A2, A1, A0
These bits determine if the input register or the control register is to be accessed.
A2
A1
A0
Function
0
NOP1
0
1
DAC input register
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Control register
D11:D0
Data bits.
1 No operation command
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