參數(shù)資料
型號(hào): EVAL-AD5390EBZ
廠商: Analog Devices Inc
文件頁數(shù): 17/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD5390
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 16
位數(shù): 14
采樣率(每秒): 125k
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 8µs
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5390
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AD5390/AD5391/AD5392
Data Sheet
Rev. E | Page 24 of 44
DATA DECODING
AD5390/AD5392
The AD5390/AD5392 contain an internal 14-bit data bus.
The input data is decoded depending on the data loaded to
the REG1 and REG0 bits of the input serial register. This is
Data from the serial input register is loaded into the addressed
DAC input register, offset (c) register, or gain (m) register. The
format data, and the offset (c) and gain (m) register contents
are shown in Table 11 to Table 13.
Table 10. Register Selection
REG1
REG0
Register Selected
1
Input data register (x1)
1
0
Offset register (c)
0
1
Gain register (m)
0
Special function registers (SFRs)
Table 11. AD5390/AD5392 DAC Data Format
(REG1 = 1, REG0 = 1)
DB13 to DB0
DAC Output (V)
11 1111
1111
2 VREF × (16383/16384)
11 1111
1111
1110
2 VREF × (16382/16384)
10 0000
0000
0001
2 VREF × (8193/16384)
10 0000
0000
2 VREF × (8192/16384)
01 1111
1111
2 VREF × (8191/16384)
00 0000
0000
0001
2 VREF × (1/16384)
00 0000
0000
0
Table 12. AD5390/AD5392 Offset Data Format
(REG1 = 1, REG0 = 0)
DB13 to DB0
Offset (LSB)
111111
1111
+8191
111111
1111
1110
+8190
100000
0000
0001
+1
100000
0000
+0
011111
1111
–1
000000
0000
0001
–8191
000000
0000
–8192
Table 13. AD5390/AD5392 Gain Data Format
(REG1 = 0, REG0 = 1)
DB13 to DB0
Gain Factor
11 1111
1111
1110
1
10 1111
1111
1110
0.75
01 1111
1111
1110
0.5
00 1111
1111
1110
0.25
00 0000
0000
0
AD5391
The AD5391 contains an internal 12-bit data bus. The input
data is decoded depending on the value loaded to the REG1 and
REG0 bits of the input serial register. The input data from the
serial input register is loaded into the addressed DAC input
register, offset (c) register, or gain (m) register. The format data
and the offset (c) and gain (m) register contents are shown in
Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0
DAC Output (V)
1111
2 VREF × (4095/4096)
1111
1110
2 VREF × (4094/4096)
1000
0000
0001
2 VREF × (2049/4096)
1000
0000
2 VREF × (2048/4096)
0111
1111
2 VREF × (2047/4096)
0000
0001
2 VREF × (1/4096)
0000
0
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0
Offset (LSB)
1111
+2047
1111
1110
+2046
1000
0000
0001
+1
1000
0000
+0
0111
1111
–1
0000
0001
–2047
0000
–2048
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0
Gain Factor
1111
1110
1
1011
1111
1110
0.75
0111
1111
1110
0.5
0011
1111
1110
0.25
0000
0
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