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參數資料
| 型號： | EVAL-AD5382EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5382 |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數量： | 32 |
| 位數： | 14 |
| 采樣率（每秒）： | 125k |
| 數據接口： | DSP，I²C，MICROWIRE?，并行，QSPI?，SPI? |
| 設置時間： | 8µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5382 |
| 其它名稱： | Q4391457 |
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AD5382
Data Sheet
Rev. C | Page 14 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
REG0
REG1
VOUT23
VOUT22
VOUT21
VOUT20
AVDD3
AGND3
DAC_GND3
SIGNAL_GND3
VOUT19
VOUT18
VOUT17
VOUT16
AVDD2
AGND2
59
74
75
69
70
71
72
67
68
66
73
64
65
60
61
62
63
57
58
55
56
53
54
52
51
NC
VOUT5
VOUT6
VOUT7
NC
MON_IN1
MON_IN2
MON_IN3
MON_IN4
NC
MON_OUT
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
DAC_GND2
SIGNAL_GND2
VOUT13
VOUT14
VOUT15
26
28
27
29
30
32
33
34
35
36
31
37
38
39
40
42
43
44
45
41
46
47
48
49
50
CS/(SYNC/AD0)
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I
2
C)
DB10
DB9
DB8
SDO(A/B)
DVDD
DGND
NC
A4
A3
A2
A1
A0
DV
DD
DV
DD
DG
ND
SER/PAR
PD
WR
(DCEN/AD1)
LDAC
BUSY
100
98
99
97
96
95
94
92
91
90
89
88
87
93
86
85
84
82
81
80
79
78
77
76
83
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
24
25
FIFO EN
CLR
VOUT24
VOUT25
VOUT26
VOUT27
SIGNAL_GND4
DAC_GND4
AGND4
AVDD4
VOUT28
VOUT29
VOUT30
VOUT31
REFGND
REFOUT/REFIN
SIGNAL_GND1
DAC_GND1
AVDD1
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
AGND1
PIN 1
IDENTIFIER
AD5382
TOP VIEW
(Not to Scale)
03733-008
Figure 8. 100-Lead LQFP Pin Configuration
Table 9. Pin Function Descriptions
Mnemonic
Function
VOUTx
Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 k to ground. Typical output impedance is 0.5 .
SIGNAL_GND(1–4)
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5382.
DAC_GND(1–4)
Ground Reference point for the Internal 14-Bit DAC. Each group of eight channels contains a DAC_GND pin. These
pins shound be connected to the AGND plane.
AGND(1–4)
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
AVDD(1–4)
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are internally shorted and
should be decoupled with a 0.1 F ceramic capacitor and a 10 F tantalum capacitor. Operating range for the
AD5382-5 is 4.5 V to 5.5 V; operating range for the AD5382-3 is 2.7 V to 3.6 V.
DGND
Ground for All Digital Circuitry.
DVDD
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 F ceramic and 10 F tantalum capacitors to DGND.
REFGND
Ground Reference Point for the Internal Reference.
REFOUT/REFIN
Reference Output when the Internal Reference is Selected. The AD5382 contains a common REFOUT/REFIN pin. If the
application requires an external reference, it can be applied to this pin, and the internal reference can be disabled
via the control register. The default for this pin is a reference input.
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