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參數(shù)資料
| 型號： | EVAL-AD5061EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION AD5061 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.3M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 4µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5061 |
AD5061
Rev. B | Page 17 of 20
AD5061-to-68HC11/68L11 Interface
Figure 42 shows a serial interface between the AD5061 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5061, while the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The set-up conditions for
correct operation of this interface require that the 68HC11/
68L11 be configured so that its CPOL bit is 0 and its CPHA bit
is 1. When data is being transmitted to the DAC, the SYNC line
is taken low (PC7). When the 68HC11/68L11 is configured
where its CPOL bit is 0 and its CPHA bit is 1, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5061, PC7 is left
low after the first eight bits are transferred, a second serial write
operation is performed to the DAC, and PC7 is taken high at
the end of this procedure.
AD50611
1ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
0
476
2-
0
32
68HC11/
68L111
Figure 42. AD5061-to-68HC11/68L11 Interface
AD5061-to-Blackfin ADSP-BF53x Interface
Figure 43 shows a serial interface between the AD5061 and the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces-
sor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5061,
the setup for the interface is: DT0PRI drives the DIN pin of
the AD5061, while TSCLK0 drives the SCLK of the part; the
SYNC is driven from TFS0.
ADSP-BF53x1
AD50611
1ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
0
476
2-
0
33
Figure 43. AD5061-to-Blackfin ADSP-BF53x Interface
AD5061-to-80C51/80L51 Interface
Figure 44 shows a serial interface between the AD5061 and the
80C51/80L51 microcontroller. The setup for the interface is:
TxD of the 80C51/80L51 drives SCLK of the AD5061 while
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to
the AD5061, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 out-
puts the serial data in a format that has the LSB first. The
AD5061 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.
80C51/80L511
AD50611
1ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04
76
2-
03
4
Figure 44. AD5061-to-80C51/80L51 Interface
AD5061-to-MICROWIRE Interface
Figure 45 shows an interface between the AD5061 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5061 on the rising edge of the SK.
MICROWIRE1
AD50611
1ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SCLK
DIN
04
76
2-
03
5
SYNC
Figure 45. AD5061-to-MICROWIRE Interface
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