- 您現在的位置：買賣IC網 > PDF目錄19512 > EPM7256AETI144-7N (Altera)IC MAX 7000 CPLD 256 144-TQFP PDF資料下載
參數資料
| 型號： | EPM7256AETI144-7N |
| 廠商： | Altera |
| 文件頁數： | 64/64頁 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 256 144-TQFP |
| 產品變化通告： | Bond Wire Change 4/Sept/2008 |
| 標準包裝： | 180 |
| 系列： | MAX® 7000A |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數目： | 16 |
| 宏單元數： | 256 |
| 門數： | 5000 |
| 輸入/輸出數： | 120 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 544-2063 EPM7256AETI144-7N-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當前第64頁
Altera Corporation
9
MAX 7000A Programmable Logic Device Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
■
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
相關PDF資料 |
PDF描述 |
|---|---|
| RS-0509D | CONV DC/DC 2W 4.5-9VIN +/-09V |
| VE-2V0-CY-F1 | CONVERTER MOD DC/DC 5V 50W |
| GNT428ABG | PWR SUP UNIV IMP 28VDC 14.3ADC |
| GEM08DRSD | CONN EDGECARD 16POS DIP .156 SLD |
| EPM7256AETI144-7 | IC MAX 7000 CPLD 256 144-TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EPM7256AFC256-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7256AFC256-12 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7256AFC256-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7256AFI256-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7256AQC208-10 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 256-CELL, 10NS PROP DELAY, 208 Pin, Plastic, QFP |
發(fā)布緊急采購，3分鐘左右您將得到回復。