參數(shù)資料
型號： EPM7064AETC44-6
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 6 ns, PQFP44
封裝： TQFP-44
文件頁數(shù)： 45/51頁
文件大?。?/td> 1559K
代理商： EPM7064AETC44-6
Altera Corporation
599
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by the Quartus and MAX+PLUS II
development systems, which are integrated packages that offer
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs, as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations. The Quartus software runs on Windows-based PCs, as well
as Sun SPARCstation and HP 9000 Series 700 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 7000A architecture includes the following elements:
s
Logic array blocks (LABs)
s
Macrocells
s
Expander product terms (shareable and parallel)
s
Programmable interconnect array
s
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7064AETC447 制造商:Altera Corporation 功能描述:
EPM7064AETC44-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AETC44-7N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AETI100-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
EPM7064AETI100-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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