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參數(shù)資料
| 型號： | EPF8482A |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 57/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8482A |
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Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Perform a complete thermal analysis before committing a design to this device package. See Application Note 74
(Evaluating Power for Altera Devices) in this data book for more information.
(2)
This pin is a dedicated pin and is not available as a user I/O pin.
(3)
SDOUT
will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the
MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and
use SDOUT as a user I/O pin.
(4)
If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.
(5)
JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.
(6)
TRST
is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.
(7)
Pin 52 is a VCC pin on EPF8452A devices only.
(8)
Unused dedicated inputs should be tied to ground on the board.
(9)
SDOUT
does not exist in the EPF8636GC192 device.
(10) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.
(11) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.
(12) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is
not used, TRST must be grounded. TMS, TDI, and TCK should be tied to VCC.
Revision
History
The information contained in the FLEX 8000 Programmable Logic Device
Family Data Sheet version 9.11 supersedes information published in
previous versions.
Version 9.11 Change
The FLEX 8000 Programmable Logic Device Family Data Sheet version 9.11
contains the following change: Figure 14 has been updated for accuracy.
No Connect
(N.C.)
–
61, 62, 119,
120, 181, 182,
239, 240
–
10, 21, 23, 25,
35, 37, 39, 40,
41, 42, 52, 55,
66, 68, 146,
147, 161, 173,
174, 176, 187,
188, 189, 190,
192, 194, 195,
205, 207, 219,
221, 233, 234,
235, 236, 302,
303
Total User I/O
Pins
148
180
177
204
Table 17. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)
Pin Name
225-Pin
BGA
EPF8820A
232-Pin
PGA
EPF81188A
240-Pin
PQFP
EPF81188A
240-Pin
PQFP
EPF81500A
280-Pin
PGA
EPF81500A
304-Pin
RQFP
EPF81500A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8636A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPF8636AGC192-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8636AGC192-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8636AGC192-4 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA |
| EPF8636AGC192-5 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA |
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