參數(shù)資料
型號： EPF6024ATC144-3
廠商： Altera
文件頁數(shù)： 16/52頁
文件大小： 0K
描述： IC FLEX 6000 FPGA 24K 144-TQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 180
系列： FLEX 6000
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 1960
輸入/輸出數(shù)： 117
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： 544-1288
Altera Corporation
23
FLEX 6000 Programmable Logic Device Family Data Sheet
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12 shows the IOE block diagram.
Figure 12. IOE Block Diagram
From LAB Local Interconnect
Slew-Rate
Control
From LAB Local Interconnect
To Row or Column Interconnect
Chip-Wide Output Enable
Delay
相關(guān)PDF資料
PDF描述
AT28HC256E-12TU IC EEPROM 256KBIT 120NS 28TSOP
AGL400V5-CS196 IC FPGA 1KB FLASH 400K 196-CSP
AT27C4096-55JU IC OTP 4MBIT 55NS 44PLCC
AT28HC256E-12JU IC EEPROM 256KBIT 120NS 32PLCC
A3P060-FGG144T IC FPGA 1KB FLASH 60K 144-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF6024ATC144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 117 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8001GM 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:10/100 LAN Interface Module with Common Mode Termination
EPF8007M 制造商:PCA 功能描述:
EPF8008 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:High Speed LAN Interface Module
EPF8008A 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:High Speed LAN Interface Module
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*