參數(shù)資料
型號： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 45/106頁
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
DS785UM1
2-5
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2.2.3.2.3
MMU Enable
Enabling the MMU allows system memory control, but is also required if the Data Cache and
the Write Buffer are to be used. Features are enabled for specific memory regions, as defined
in the system page table. MMU enablement is done via CP15 register 1. The procedure is as
follows:
1. Program the Translation Table Base (TTB) and domain access control registers
2. Create level 1 and level 2 pages for the system, and enable the Data Cache and the
Write Buffer
3. Enable the MMU via bit 0 of CP15 register 1.
2.2.3.3 Cache and Write Buffer
Cache configuration is 64-way set associative. There is a 16 kbyte instruction cache and a 16
kbyte data cache. The caches have the following characteristics:
8 words per line, with 1 valid bit and 2 dirty bits per line to allow half-line write-backs
Write-through or write-back capability, selectable per memory region defined by the
MMU
Pseudo random or round robin replacement algorithms for cache misses. This is
determined by the RR bit (bit 14) in CP15 register 1. On a cache miss (instruction or data
not in the respective cache), an 8-word line is fetched from memory and loaded into the
cache
Independent cache lock-down with granularity of 1/64th of total cache size or 256 bytes
for both instructions and data. Lock-down of the cache will prevent an eight-word cache
line fill into that region of the cache
For compatibility with Windows CE and to reduce latency, physical addresses for data
cache entries are stored in the PA TAG RAM, which is used for cache line write-back
operations without need of the MMU. This prevents a possible TLB miss that would
degrade performance
The Write Buffer has a depth of 16 data words. If enabled, writes are sent to the Write
Buffer directly from the Data Cache or from the CPU (in the event of a cache miss or if
the cache is not enabled).
2.2.3.3.1
Instruction Cache Enable
At reset, the Instruction Cache is disabled
A write to bit 12 of CP15 register 1 will enable or disable the Instruction Cache. If the
Instruction Cache (I-Cache) is enabled without the MMU enabled, all accesses are
treated as cacheable
If the I-Cache is disabled, current contents are ignored. If re-enabled before a reset,
contents will be unchanged, but may not be coherent with eternal memory. If so,
contents must be flushed before re-enabling.
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