鍨嬭櫉(h脿o)锛� | EP2S30F672C4 |
寤犲晢锛� | Altera |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 116/768闋�(y猫) |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC STRATIX II FPGA 30K 672-FBGA |
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 10 |
绯诲垪锛� | Stratix® II |
LAB/CLB鏁�(sh霉)锛� | 1694 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 33880 |
RAM 浣嶇附瑷�(j矛)锛� | 1369728 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 500 |
闆绘簮闆诲锛� | 1.15 V ~ 1.25 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 672-BBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 672-BGA锛�27x27锛� |
鍏跺畠鍚嶇ū锛� | 544-1125 |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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EP20K300EQC240-1 | IC APEX 20KE FPGA 300K 240-PQFP |
RBB110DHAT | CONN EDGECARD 220PS R/A .050 DIP |
EP20K200EFC672-1 | IC APEX 20KE FPGA 200K 672-FBGA |
ASC50DRTF | CONN EDGECARD 100PS .100 DIP SLD |
EP1S25B672C7N | IC STRATIX FPGA 25K LE 672-BGA |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP2S30F672C4N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C5 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C5AA | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix |
EP2S30F672C5N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C5RB | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix |