參數(shù)資料
型號： EP20K60EQC240
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP240
封裝： 34.90 X 34.90 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁數(shù)： 95/114頁
文件大?。?/td> 4116K
代理商： EP20K60EQC240
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-67
Table 2-93 IGLOO nano CCC/PLL Specification
For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
160
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
160
MHz
Delay Increments in Programmable Delay Blocks 1, 2
580
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL 5
60
MHz
Input Cycle-to-Cycle Jitter (peak magnitude)
0.25
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
External
FB Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.75%
0.70%
24 MHz to 100 MHz
1.00%
1.50%
1.20%
100 MHz to 160 MHz
2.50%
3.75%
2.75%
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter
LockControl = 0
4
ns
LockControl = 1
3
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
2.3
20.86
ns
Delay Range in Block: Programmable Delay 2 1, 2,
0.025
20.86
ns
Delay Range in Block: Fixed Delay 1, 2
5.7
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for deratings.
2. TJ = 25°C, VCC = 1.2 V
3. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
5. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for derating values.
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EP20K60EQC240-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60EQC240-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K60EQC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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