參數(shù)資料
型號: EP20K60EFC484
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PBGA484
封裝: 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484
文件頁數(shù): 82/114頁
文件大小: 4116K
代理商: EP20K60EFC484
Altera Corporation
7
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 7. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
Full support
Hot-socketing support
Full support
SignalTap logic analysis
Full support
64-Bit, 66-MHz PCI
Full compliance
MultiVolt I/O
2.5-V or 3.3-V VCCIO
VCCIO selected for device
1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO selected block-by-block
ClockLock support
Clock delay reduction
2
× and 4× clock multiplication
Clock delay reduction
m /(n
× v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Six
Eight
I/O standard support
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
1.8-V, 2.5-V, 3.3-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVDS and LVPELL data pins (in
EP20K300E and larger devices)
LVDS and LVPELL clock pins (in all
devices)
LVTTL
HSTL Class I
LVPECL
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
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