參數(shù)資料
型號: EP20K200CP208C9
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 40/114頁
文件大?。?/td> 1623K
代理商: EP20K200CP208C9
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
ESB
to System Logic
Address Decoder
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
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EP20K200CP208I7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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