參數(shù)資料
型號： EP20K100QC240-2
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 31/114頁
文件大小： 1623K
代理商： EP20K100QC240-2
Altera Corporation
23
APEX 20K Programmable Logic Device Family Data Sheet
Figure 11 shows the intersection of a row and column interconnect, and
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
APEX 20KE devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow interconnect, which routes signals directly into the local
interconnect without having to drive through the MegaLAB interconnect.
FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K300E
and larger devices, the FastRow interconnect drives the two MegaLABs in
the top left corner and the two MegaLABs in the bottom right corner. On
EP20K200E and smaller devices, FastRow interconnect drives the two
MegaLABs on the top and the two MegaLABs on the bottom of the device.
On all devices, the FastRow interconnect drives all local interconnect in
the appropriate MegaLABs except the interconnect areas on the far left
and far right of the MegaLAB. Pins using the FastRow interconnect
achieve a faster set-up time, as the signal does not need to use a MegaLab
interconnect line to reach the destination LE. Figure 12 shows the FastRow
interconnect.
Row Interconnect
MegaLAB Interconnect
LE
Column
Interconnect
Local
Interconnect
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100QC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QC2403 制造商:Altera 功能描述:_
EP20K100QC240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100QC240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QC240-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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