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參數資料
| 型號： | EP20K100QC208-1ES |
| 英文描述： | White LED Driver with PWM Dimming; Temperature Range: -40°C to 85°C; Package: 8-TDFN T&R |
| 中文描述： | FPGA的 |
| 文件頁數： | 66/114頁 |
| 文件大小： | 1623K |
| 代理商： | EP20K100QC208-1ES |
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Altera Corporation
55
APEX 20K Programmable Logic Device Family Data Sheet
SignalTap
Embedded
Logic Analyzer
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All APEX 20K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. The EP20K1500E device supports the
JTAG BYPASS instruction and the SignalTap instructions. JTAG
boundary-scan testing can be performed before or after configuration, but
not during configuration. APEX 20K devices can also use the JTAG port
for configuration with the Quartus II software or with hardware using
either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Finally, APEX 20K
devices (except the EP20K1500E) use the JTAG port to monitor the logic
operation of the device with the SignalTap embedded logic analyzer.
APEX 20K devices support the JTAG instructions shown in Table 19.
Note:
(1)
The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions.
Table 19. APEX 20K JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins. Also used by the SignalTap embedded logic analyzer.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through selected devices to adjacent devices during
normal device operation.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO.
ICR Instructions
Used when configuring an APEX 20K device via the JTAG port with a MasterBlasterTM
or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File
via an embedded processor.
SignalTap Instructions
Monitors internal device operation with the SignalTap embedded logic analyzer.
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PDF描述 |
|---|---|
| EP20K100QC208-2 | Field Programmable Gate Array (FPGA) |
| EP20K100QC208-2ES | FPGA |
| EP20K100QC208-3 | Field Programmable Gate Array (FPGA) |
| EP20K100QC208-3ES | FPGA |
| EP20K100QC240-1 | Field Programmable Gate Array (FPGA) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EP20K100QC208-1X | 制造商:Altera Corporation 功能描述:IC FPGA 159 I/O 208QFP 制造商:Altera Corporation 功能描述:IC APEX 20K FPGA 208QFP |
| EP20K100QC208-2 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 159 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100QC208-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100QC208-2X | 制造商:Altera Corporation 功能描述:IC APEX 20K FPGA 208PQFP |
| EP20K100QC208-3 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 159 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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