參數(shù)資料
型號： EP20K100ERC240-1ES
元件分類： 數(shù)字電位計
英文描述： Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
中文描述： FPGA的
文件頁數(shù)： 82/114頁
文件大?。?/td> 1623K
代理商： EP20K100ERC240-1ES
Altera Corporation
7
APEX 20K Programmable Logic Device Family Data Sheet
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
Full support
SignalTap logic analysis
Full support
32/64-Bit, 33-MHz PCI
Full compliance in -1, -2 speed
grades
Full compliance in -1, -2 speed grades
32/64-Bit, 66-MHz PCI
-
Full compliance in -1 speed grade
MultiVolt I/O
2.5-V or 3.3-V VCCIO
VCCIO selected for device
Certain devices are 5.0-V tolerant
1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO selected block-by-block
5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
2
× and 4× clock multiplication
Clock delay reduction
m /(n
× v) or m/(n × k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Six
Eight
I/O standard support
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL clock pins (in all
devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
相關(guān)PDF資料
PDF描述
EP20K100ERC240-2ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K100ERC240-3ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-TDFN
EP20K100ETC144-2ES FPGA
EP20K100ETC144-3ES 128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 8-DFN
EP20K100ETI144-1ES FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100ERC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ERC240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ERI208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ERI208-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100ERI208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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