參數資料
型號: EP20K100BI356-1ES
英文描述: Charging System Safety Circuit; Temperature Range: -40°C to 85°C; Package: 12-DFN T&R
中文描述: FPGA的
文件頁數: 61/114頁
文件大?。?/td> 1623K
代理商: EP20K100BI356-1ES
50
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 30. Specifications for the Incoming & Generated Clocks
The tI parameter refers to the nominal input clock period; the tO parameter refers to the
nominal output clock period.
Table 15 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -1 speed-grade devices.
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade
Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
180
MHz
fCLK1 (1)
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
180
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
90
MHz
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
10
48
MHz
tOUTDUTY
Duty cycle for
ClockLock/ClockBoost-generated
clock
40
60
%
fCLKDEV
Input deviation from user
specification in the Quartus II
software (ClockBoost clock
multiplication factor equals 1) (2)
25,000
PPM
tR
Input rise time
5
ns
tF
Input fall time
5
ns
Input
Clock
ClockLock
Generated
Clock
f CLK1 f CLK2
f CLK4
t INDUTY
t I + t CLKDEV
t R
t F
t O
t I + t INCLKSTB
t O
tO
t JITTER
tO + t JITTER
t OUTDUTY
,,
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相關代理商/技術參數
參數描述
EP20K100BI356-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100BI356-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100BI356-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100BI356-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100E 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family