參數(shù)資料
型號： EP20K1000CF672I9ES
元件分類： 數(shù)字電位計
英文描述： Single Digitally Controlled Potentiometer (XDCP™), Low Noise/Low Power/I2C Bus/256 Taps; Temperature Range: -25°C to 85°C; Package: 8-MSOP
中文描述： 專用集成電路
文件頁數(shù)： 20/114頁
文件大?。?/td> 1623K
代理商： EP20K1000CF672I9ES
Altera Corporation
13
APEX 20K Programmable Logic Device Family Data Sheet
Logic Element
The LE, the smallest unit of logic in the APEX 20K architecture, is compact
and provides efficient logic usage. Each LE contains a four-input LUT,
which is a function generator that can quickly implement any function of
four variables. In addition, each LE contains a programmable register and
carry and cascade chains. Each LE drives the local interconnect, MegaLAB
interconnect, and FastTrack Interconnect routing structures. See Figure 5.
Figure 5. APEX 20K Logic Element
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
labclk1
labclk2
labclr1
labclr2
Carry-In
Clock &
Clock Enable
Select
Carry-Out
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
labclkena1
labclkena2
Synchronous
Load & Clear
Logic
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4
相關(guān)PDF資料
PDF描述
EP20K1000EBC652-1ES Single Digitally Controlled Potentiometer (XDCP™), Low Noise/Low Power/I2C Bus/256 Taps; Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K1000EBC652-2ES Single Digitally Controlled Potentiometer (XDCP™), Low Noise/Low Power/I2C Bus/256 Taps; Temperature Range: -40°C to 85°C; Package: 8-MSOP T&R
EP20K1000EBC652-3ES FPGA
EP20K1000EBI652-1ES Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 20-TSSOP
EP20K1000EBI652-2ES Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -25°C to 85°C; Package: 20-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K1000E 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EP20K1000EBC652-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EBC652-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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