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參數(shù)資料
| 型號： | EL4511CUZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID SYNC SEPARATR HDTV 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | 同步分離器 |
| 應(yīng)用： | HDTV，投影儀，機頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
24
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7009.8
November 12, 2010
Application 3 (application using a microcontroller
interface)
In this example, the requirement is to provide the
synchronizing information in a video digitizing interface. This
example is very similar to the example in application 2. In
this example the incoming sync signals may come from one
of three sources. Computer, HDTV source or an NTSC/PAL
device.
As there is a Microcontroller connected in this example, a
32.768kHz XTAL is connected to pins 1 & 24; this will allow
the system microcontroller to gather timing information for
the vertical rate. To enable the crystal oscillator, register 9,
bit 6 must be set to a high.
Note that a Low Pass Filter is in the NTSC/PAL signal path to
reduce noise, glitches and subcarrier. (In signals with bad
Croma/Luma gain balance, the subcarrier can extend into
the sync slicing level).
As some of the signals in this application were non standard
formats, the fixed slice mode is used by setting register 2,
bit 5 to a high. Register 1, bit 6 is also set to a high. This
forced the EL4511 to provide outputs even when the input
signals are not recognized by the internal algorithms.
FIGURE 12. APPLICATIONS DRAWING 3
9
XTALN
11
10
4
1
24
XTAL
PDWN
SYNCIN
VERTIN
HIN
8
GNDD1
13
GNDA2
17
GNDD2
6
SCL
7
SDA
14
18
15
V
CCA1
VCCD
V
CCA2
16
+
22
21
GNDA2
VERTOUT
HOUT
4.7F
0.1F
100nF
VCC
0.1F
VERTICAL
TIMING
HORIZONTAL
TIMING
EL4511
VIDEO SIGNAL (CVBS)
VIDEO SIGNALS (HDTV)
VIDEO SIGNALS (RGB)
H SYNC
V SYNC
HDTV
SYNCS
CVBS
75
Ω
75
Ω
75
Ω
75
Ω
620
Ω
510pF
COMPONENT
COMPOSITE
SDENB
5
TO MICROCONTROLLER
20
2
BACKPORCH
VBLANK
VIDEO
CLAMP
PLL
COAST
32.768kHz
CRYSTAL
EL4511
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