11
EL4331C
Triple 2:1 Mux-Amp AV = 1
EL
4331C
Applications Information
High Speed 8-to-1 Multiplexer
Note: No supply bypass capacitors shown and only one
of three channels shown.
Channel Selection Table
BIT2BIT1BIT0OUTPUT
000SIG0
001SIG1
010SIG2
011SIG3
100SIG4
101SIG5
110SIG6
111SIG7
Figure 3. A High Speed, 8:1 Component Video
Multiplexer
Photograph A3 shows the same circuit, with the counter
running at 25 MHz. This turns out to be close to the limit
of the TTL counter used in the breadboard, rather than
the limit of the EL4331. Here the different glitches are
easily recognizable—a small glitch for one of the 4 input
EL4331s A/B switching, somewhat larger glitches when
two banks switch together, and the biggest glitch when
all three banks switch. Photograph A4 shows the big
glitch in detail. A good PCB and equal length and
matched traces would clean up these glitches.
433129
A1
433130
A2
433131
A3
433132
A4
8-to-1 Multiplexer using Power Down
Note: No supply bypass capacitors shown. Only one of
three channels shown.
Channel Selection Table
BIT2BIT1BIT0OUTPUT
000SIG0
001SIG1
010SIG2
011SIG3
100SIG4
101SIG5
110SIG6
111SIG7
Figure 4. A Simple 8:1 Component Video Multiplexer
Figure 4 shows one of the three channels of a component
video, 8:1 multiplexer. In this example, the power down
capability is used to save on EL4331s, but as can be
seen, the control part does become more complicated.
Using the power down mode for multiplexing does, of
course, slow down the speed with which one can select a
given input channel. However, if input channel selection
can be done during a blanking period, the couple of
microseconds that it takes to power down one
chip may be no problem. Note that some external logic
is needed in this application, both to select the appropri-
ate amplifier, and also to force a break-before-make
action by pulling the T_OFF line low. All this logic
would best be incorporated inside a PAL or gate array,
and is shown in gate form just to illustrate the idea. Note
that the BIT0 line would have the 3 ns response time,
since it is switching the muxamps directly.
Photograph B1 shows a staircase generated by having all
the inputs (sig0 through sig7) connected to a resistive
divider chain, and then the select bits and the PD pins
were driven by a binary counter and a 2-line to 1 of 4
decoder. Photograph B2 shows the glitch between steps
4 and 5; this glitch is caused by the fact that the amplifier
that has just been powered up momentarily fights the
amplifier that has been powered down, but is not yet off.
As seen in the photograph, this causes a glitch of about
200 ns duration. However, when the A/B select pin
changes inputs, the glitches are much smaller, as shown
in photograph B3. Photograph B4 shows the +2.5V to