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| 型號： | EFM32-TG-STK3300 |
| 廠商： | Energy Micro |
| 文件頁數(shù)： | 130/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT STARTER EFM32 GECKO |
| 特色產(chǎn)品： | EFM32 Tiny Gecko |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | EFM®32 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | EFM32-TGXXX |
| 所含物品： | 板，線纜，CD 和文檔 |
| 其它名稱： | 914-1018 |
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
93
www.energymicro.com
byte offset 2 refers to register bits[23:16]
byte offset 3 refers to register bits[31:24].
4.2.8 Software Trigger Interrupt Register
Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in
Table 4.2 (p. 88) for the STIR attributes.
When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see
Note
Only privileged software can enable unprivileged access to the STIR.
The bit assignments are:
9
31
0
Reserved
INTID
8
Table 4.10. STIR bit assignments
Bits
Field
Function
[31:9]
-
Reserved.
[8:0]
INTID
Interrupt ID of the required SGI, in the range 0 to (n-1), where n denotes the number of interrupts given
by Table 1.1 (p. 5) . For example, a value of b000000011 specifies interrupt IRQ3.
4.2.9 Level-sensitive interrupts
All interrupt lines in the EFM32 devices are level sensitive interrupts. A level-sensitive interrupt is held
asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR
accesses the peripheral, causing it to clear the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt, see
Section 4.2.9.1 (p. 93) . If the signal is not deasserted before the processor returns from the ISR, the
interrupt becomes pending again, and the processor must execute its ISR again. This means that the
peripheral can hold the interrupt signal asserted until it no longer needs servicing.
4.2.9.1 Hardware and software control of interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see Section 4.2.4 (p. 90) ,
or to the STIR to make an SGI pending, see Section 4.2.8 (p. 93) .
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending
to active. Then:
When the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal
is asserted, the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EFM32TG-STK3300 | 制造商:Energy Micro AS 功能描述:STARTER KIT STK3300 TINY GEC 制造商:Energy Micro AS 功能描述:STARTER KIT, STK3300, TINY GECKO; Silicon Manufacturer:Energy Micro; Core Architecture:ARM; Core Sub-Architecture:Cortex-M3; Silicon Core Number:EFM32TG840; Silicon Family Name:EFM32; Kit Contents:Starter Kit EFM32TG840; SVHC:No SVHC;RoHS Compliant: Yes |
| EFM32WG230F128 | 功能描述:ARM微控制器 - MCU 128kb flash 32kb RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| EFM32WG230F128-QFN64 | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, WONDER GECKO - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64QFN |
| EFM32WG230F128-QFN64T | 制造商:Energy Micro AS 功能描述:WONDER GECKO 32 BIT ARM CORTEX MCU - Trays |
| EFM32WG230F128-QFN64-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64QFN |
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