參數(shù)資料
型號(hào): EFM32-TG-STK3300
廠商: Energy Micro
文件頁數(shù): 128/136頁
文件大小: 0K
描述: KIT STARTER EFM32 GECKO
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: EFM®32
類型: MCU
適用于相關(guān)產(chǎn)品: EFM32-TGXXX
所含物品: 板,線纜,CD 和文檔
其它名稱: 914-1018
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
91
www.energymicro.com
Table 4.6. ISPR bit assignments
Bits
Name
Function
[31:0]
SETPEND
Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to
pending.Read:
0 = interrupt is not pending
1 = interrupt is pending.
Note
Writing 1 to the ISPR bit corresponding to:
an interrupt that is pending has no effect
a disabled interrupt sets the state of that interrupt to pending.
4.2.5 Interrupt Clear-pending Registers
The ICPR0 and ICPR1 registers remove the pending state from interrupts, and show which interrupts
are pending. See:
the register summary in Table 4.2 (p. 88) for the register attributes
Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
CLRPEND bit s
31
0
Table 4.7. ICPR bit assignments
Bits
Name
Function
[31:0]
CLRPEND
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an
interrupt.Read:
0 = interrupt is not pending
1 = interrupt is pending.
Note
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
4.2.6 Interrupt Active Bit Registers
The IABR0 and IABR1 registers indicate which interrupts are active. See:
the register summary in Table 4.2 (p. 88) for the register attributes
Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
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