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參數(shù)資料
| 型號： | EDS1232AABB-60 |
| 英文描述： | Programmable VCOM; Temperature Range: -40°C to 85°C; Package: 24-QFN |
| 中文描述： | 內(nèi)存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料 |
| 文件頁數(shù)： | 13/55頁 |
| 文件大?。?/td> | 570K |
| 代理商： | EDS1232AABB-60 |
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EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
20
Current state
/CS
/RAS /CAS /WE Address
Command
Operation
Notes
Write recovering
H
×
DESL
Nop
→ Enter row active after tDPL
L
H
×
NOP
Nop
→ Enter row active after tDPL
L
H
L
×
BST
Nop
→ Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
BA, CA, A10
WRIT/ WRITA
New write, Determine AP
L
H
BA, RA
ACT
ILLEGAL
3
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
H
×
REF/SELF
ILLEGAL
L
OPCODE
MRS
ILLEGAL
Write recovering
H
×
DESL
Nop
→ Enter precharge after tDPL
with auto
L
H
×
NOP
Nop
→ Enter precharge after tDPL
precharge
L
H
L
×
BST
Nop
→ Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3, 8
L
H
BA, RA
ACT
ILLEGAL
3
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
H
×
REF/SELF
ILLEGAL
L
OPCODE
MRS
ILLEGAL
Refresh
H
×
DESL
Nop
→ Enter idle after tRC
L
H
×
NOP/BST
Nop
→ Enter idle after tRC
L
H
L
×
READ/READA
ILLEGAL
L
H
L
H
×
ACT/PRE/PALL ILLEGAL
L
H
L
×
REF/SELF/MRS ILLEGAL
Mode register
H
×
DESL
Nop
→ Enter idle after tRSC
accessing
L
H
×
NOP
Nop
→ Enter idle after tRSC
L
H
L
×
BST
ILLEGAL
L
H
L
H
×
READ/READA
ILLEGAL
L
×
ACT/PRE/PLL/
REF/SELF/MRS
ILLEGAL
Remark:
H: VIH. L: VIL.
×: VIH or VIL, V = Valid data
BA: Bank Address, CA: Column Address, RA: Row Address
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down
mode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EDS1232AABB-60-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
| EDS1232AABB-60L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| EDS1232AABB-60L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
| EDS1232AABB-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| EDS1232AABB-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
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