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參數(shù)資料
| 型號： | EDL1216CASA-10 |
| 英文描述： | Programmable VCOM; Temperature Range: -40°C to 85°C; Package: 24-QFN |
| 中文描述： | 內(nèi)存| 4X2MX16 |的CMOS | BGA封裝| 54PIN |塑料 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 489K |
| 代理商： | EDL1216CASA-10 |
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EDL1216AASA
Data Sheet E0196E20 (Ver. 2.0)
27
Read / Write Command Interval
Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed.
READ will be interrupted by another READ.
The interval between the
commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
QB1
QB2
QB3
QB4
Hi-Z
READ A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
READ B
QA1
1cycle
T9
Read to Read Command Interval
Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command.
WRITE will be interrupted by another WRITE.
The interval between the
commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.
DB1
DB2
DB3
DB4
Hi-Z
WRITE A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
WRITE B
DA1
1cycle
Write to Write Command Interval
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