參數(shù)資料
型號(hào): EDI816256CA20M44I
英文描述: x16 SRAM
中文描述: x16的SRAM
文件頁數(shù): 3/5頁
文件大?。?/td> 107K
代理商: EDI816256CA20M44I
3
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA-RP
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-15
-17
-20
-25
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
ns
Address Access Time
tAA
15
17
20
25
ns
Output Hold from Address Change
tOH
000
0
ns
Chip Select Access Time
tACS
15
17
20
25
ns
Output Enable to Output Valid
tOE
10
12
ns
Chip Select to Output in Low Z
tCLZ1
555
5
ns
Output Enable to Output in Low Z
tOLZ1
000
0
ns
Chip Disable to Output in High Z
tCHZ1
77
7
8
ns
Output Disable to Output in High Z
tOHZ1
77
7
8
ns
LB, UB Access Time
tBA
10
12
ns
LB, UB Enable to Low Z Output
tBLZ1
000
0
ns
LB, UB Disable to High Z Output
tBHZ1
77
7
8
ns
1. This parameter is guaranteed by design but not tested.
I
Current Source
D.U.T.
C
= 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-15
-17
-20
-25
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
ns
Chip Select to End of Write
tCW
12
15
17
ns
Address Valid to End of Write
tAW
12
15
17
ns
Data Valid to End of Write
tDW
10
12
ns
Write Pulse Width
tWP
12
15
17
ns
Address Setup Time
tAS
00
ns
Address Hold Time
tAH
00
ns
Output Active from End of Write
tOW1
00
ns
Write Enable to Output in High Z
tWHZ1
888
8
ns
Data Hold Time
tDH
00
ns
LB, UB Valid to End of Write
tBW
12
15
16
18
ns
1. This parameter is guaranteed by design but not tested.
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