參數(shù)資料
型號(hào)： EDE5108AJBG-8E-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 512M bits DDR2 SDRAM
中文描述： 64M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù)： 33/77頁(yè)
文件大?。?/td> 589K
代理商： EDE5108AJBG-8E-E
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
33
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Note
Extended Mode
H
×
×
×
×
DESL
Nop -> Enter idle after tMRD
register accessing L
H
H
H
×
NOP
Nop -> Enter idle after tMRD
L
H
L
H
BA, CA, A10 (AP)
READ/READA ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRIT/WRITA ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA
PRE
ILLEGAL
L
L
H
L
A10 (AP)
PALL
ILLEGAL
L
L
L
H
×
REF
ILLEGAL
L
L
L
H
×
SELF
ILLEGAL
L
L
L
L
BA, MRS-OPCODE
MRS
ILLEGAL
Remark: H = VIH. L = VIL.
×
= VIH or VIL
Notes: 1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruptions at other timings are illegal.
5. Available in case tRCD is satisfied by AL setting.
6. Available in case tWTR is satisfied.
7. The DDR2 SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge
enabled,or a write with auto-precharge enabled, may be followed by any column command to other
banks, as long as that command does not interrupt the read or write data transfer, and all other related
limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.)
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
From command
interrupting command)
L
L
L
L
BA, EMRS-OPCODE
EMRS (1) (2)
ILLEGAL
To command (different bank, non-
Minimum delay
(Concurrent AP supported)
Units
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
(BL/2) + 2
tCK
Precharge or Activate
1
tCK
Write w/AP
Read or Read w/AP
(CL
1) + (BL/2) + tWTR
tCK
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
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