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參數(shù)資料
| 型號： | EDE5108AJBG-8E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 64M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 1/77頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDE5108AJBG-8E-E |
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Document No. E1044E20 (Ver. 2.0)
Date Published May 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5108AJBG (64M words
×
8 bits)
EDE5116AJBG (32M words
×
16 bits)
Specifications
Density: 512M bits
Organization
16M words
×
8 bits
×
4 banks (EDE5108AJBG)
8M words
×
16 bits
×
4 banks (EDE5116AJBG)
Package
60-ball FBGA (EDE5108AJBG)
84-ball FBGA (EDE5116AJBG)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
Data rate: 800Mbps/667Mbps (max.)
1KB page size (EDE5108AJBG)
Row address: A0 to A13
Column address: A0 to A9
2KB page size (EDE5116AJBG)
Row address: A0 to A12
Column address: A0 to A9
Four internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8
μ
s at 0
°
C
≤
TC
≤
+
85
°
C
3.9
μ
s at
+
85
°
C
<
TC
≤
+
95
°
C
Operating case temperature range
TC = 0
°
C to +95
°
C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDE5108AJSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108GASA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5108GASA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
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