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參數(shù)資料
| 型號(hào)： | EDD1232AAFA-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M bits DDR SDRAM (4M words x 32 bits) |
| 中文描述： | 4M X 32 DDR DRAM, 0.7 ns, PQFP100 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 8/50頁 |
| 文件大小： | 621K |
| 代理商： | EDD1232AAFA-6B-E |
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EDD1232AABH
Data Sheet E0533E50 (Ver. 5.0)
8
-6B
-7A
Parameter
Auto refresh to Active/Auto refresh command
period
Symbol
min.
max.
min.
max.
Unit
Notes
tRFC
72
—
75
—
ns
Active to Read delay
tRCDRD
18
—
20
—
ns
Active to Write delay
tRCDWR
12
—
15
—
ns
Precharge to active command period
tRP
18
—
20
—
ns
Active to Autoprecharge delay
tRAP
tRCDRD min. —
tRCDRD min. —
ns
Active to active command period
tRRD
12
—
15
—
ns
Write recovery time
tWR
18
—
20
—
ns
Auto precharge write recovery and
precharge time
tDAL
6
—
6
—
tCK
Internal write to Read command delay
tWTR
2
—
2
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
μs
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1232AAFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232ABBH | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ABBH-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ACBH | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ACBH-5B-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
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