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參數(shù)資料
| 型號： | EBD21RD4ADNA-7A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 201K |
| 代理商： | EBD21RD4ADNA-7A-E |
EBD21RD4ADNA-E
Data Sheet E0606E10 (Ver. 1.0)
13
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max
min.
max.
Unit Notes
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK 9
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
0.35
—
0.35
—
tCK
Address and control input setup time tIS
0.75
—
0.9
—
0.9
—
ns
8
Address and control input hold time
tIH
0.75
—
0.9
—
0.9
—
ns
8
Address and control input pulse width tIPW
2.2
—
2.2
—
2.2
—
ns
7
Mode register set command cycle
time
tMRD
2
—
2
—
2
—
tCK
Active to Precharge command period tRAS
42
120000
45
120000
45
120000
ns
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
tRC
60
—
65
—
65
—
ns
tRFC
72
—
75
—
75
—
ns
Active to Read/Write delay
tRCD
18
—
20
—
20
—
ns
Precharge to active command period tRP
18
—
20
—
20
—
ns
Active to Autoprecharge delay
tRAP
tRCD min. —
tRCD min. —
tRCD min. —
ns
Active to active command period
tRRD
12
—
15
—
15
—
ns
Write recovery time
tWR
15
—
15
—
15
—
ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
tDAL
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
tCK 13
tWTR
1
—
1
—
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
—
7.8
μs
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EBD21RD4ADNA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD24A | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:EURO BLOCKS TS & EB SERIES |
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