參數(shù)資料
型號(hào)： DSPIC30F4011-20E/ML
廠商： Microchip Technology
文件頁(yè)數(shù)： 38/238頁(yè)
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 48K 44QFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 45
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲(chǔ)器容量： 48KB（16K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 管件
其它名稱： DSPIC30F401120EML
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dsPIC30F4011/4012
DS70135G-page 132
2010 Microchip Technology Inc.
19.4
Message Reception
19.4.1
RECEIVE BUFFERS
The CAN bus module has 3 receive buffers. However,
one of the receive buffers is always committed to mon-
itoring the bus for incoming messages. This buffer is
called the message assembly buffer (MAB). There are
two receive buffers, visibly denoted as RXB0 and
RXB1, that can essentially instantaneously receive a
complete message from the protocol engine.
All messages are assembled by the MAB, and are
transferred to the RXBn buffers only if the acceptance
filter criterion is met. When a message is received, the
RXxIF flag (C1INTF<0> or C1INIF<1>) will be set. This
bit can only be set by the module when a message is
received. The bit is cleared by the CPU when it has
completed processing the message in the buffer. If the
RXxIE bit (C1INTE<0> or C1INTE<1>) is set, an
interrupt will be generated when a message is
received.
RXF0 and RXF1 filters with the RXM0 mask are
associated with RXB0. The filters, RXF2, RXF3, RXF4
and RXF5, and the mask, RXM1, are associated with
RXB1.
19.4.2
MESSAGE ACCEPTANCE FILTERS
The message acceptance filters and masks are used to
determine if a message in the message assembly buf-
fer should be loaded into either of the receive buffers.
Once a valid message has been received into the Mes-
sage Assembly Buffer (MAB), the identifier fields of the
message are compared to the filter values. If there is a
match, that message will be loaded into the appropriate
receive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (C1RXFxSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame
and only filters with the EXIDE bit set are compared.
19.4.3
MESSAGE ACCEPTANCE FILTER
MASKS
The mask bits essentially determine which bits to apply
the filter to. If any mask bit is set to a zero, then that bit
will automatically be accepted regardless of the filter
bit. There are 2 programmable acceptance filter masks
associated with the receive buffers, one for each buffer.
19.4.4
RECEIVE OVERRUN
An overrun condition occurs when the Message
Assembly Buffer (MAB) has assembled a valid
received message, the message is accepted through
the acceptance filters, and when the receive buffer
associated with the filter has not been designated as
clear of the previous message.
The overrun error flag, RXxOVR (C1INTF<15> or
C1INTF<14>) and the ERRIF bit (C1INTF<5>) will be
set and the message in the MAB will be discarded.
If the DBEN bit is clear, RXB1 and RXB0 operate inde-
pendently. When this is the case, a message intended
for RXB0 will not be diverted into RXB1 if RXB0
contains an unread message and the RX0OVR bit will
be set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid message is received for RXB0 and
RXFUL = 1, it indicates that RXB0 is full and
RXFUL = 0 indicates that RXB1 is empty, the message
for RXB0 will be loaded into RXB1. An overrun error will
not be generated for RXB0. If a valid message is
received for RXB0 and RXFUL = 1, and RXFUL = 1
indicates that both RXB0 and RXB1 are full, the
message will be lost and an overrun will be indicated
for RXB1.
19.4.5
RECEIVE ERRORS
The CAN module will detect the following receive
errors:
Cyclic Redundancy Check (CRC) Error
Bit Stuffing Error
Invalid Message Receive Error
The receive error counter is incremented by one in
case one of these errors occur. The RXWAR bit
(C1INTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
19.4.6
RECEIVE INTERRUPTS
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
19.4.6.1
Receive Interrupt
A message has been successfully received and loaded
into one of the receive buffers. This interrupt is acti-
vated immediately after receiving the End-of-Frame
(EOF) field. Reading the RXxIF flag will indicate which
receive buffer caused the interrupt.
19.4.6.2
Wake-up Interrupt
The CAN module has woken up from Disable mode or
the device has woken up from Sleep mode.
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DSPIC30F4011-20I/ML 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 Bit MCU/DSP 44LD 20M 48KB FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F4011-20I/ML 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller Memory
DSPIC30F4011-20I/P 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16bit Signal Cntrlr RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F4011-20I/P 制造商:Microchip Technology Inc 功能描述:16BIT MCU-DSP 20MHZ 30F4011 DIP40
DSPIC30F4011-20I/PT 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 Bit MCU/DSP 20M 48KB FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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