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2010
Micr
och
ip
T
e
chn
o
logy
Inc.
DS70135G-pa
g
e
127
dsPIC30F401
1/4012
TABLE 18-1:
UART1 REGISTER MAP(1)
TABLE 18-2:
UART2 REGISTER MAP (NOT AVAILABLE ON dsPIC30F4012)(1)
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
U1MODE
020C
UARTEN
—USIDL
—
—ALTIO
—
WAKE
LPBACK
ABAUD
—
PDSEL1 PDSEL0
STSEL 0000 0000 0000 0000
U1STA
020E
UTXISEL
—
UTXBRK
UTXEN
UTXBF
TRMT
URXISEL1 URXISEL0 ADDEN
RIDLE
PERR
FERR
OERR
URXDA 0000 0001 0001 0000
U1TXREG
0210
—
UTX8
Transmit Register
0000 000u uuuu uuuu
U1RXREG
0212
—
URX8
Receive Register
0000 0000 0000 0000
U1BRG
0214
Baud Rate Generator Prescaler
0000 0000 0000 0000
Legend:
u
= uninitialized bit; — = unimplemented bit, read as ‘0’
Note
1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
U2MODE
0216
UARTEN
—USIDL
—
WAKE
LPBACK
ABAUD
—
PDSEL1 PDSEL0
STSEL
0000 0000 0000 0000
U2STA
0218
UTXISEL
—
UTXBRK UTXEN
UTXBF
TRMT
URXISEL1 URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA 0000 0001 0001 0000
U2TXREG
021A
—
UTX8
Transmit Register
0000 000u uuuu uuuu
U2RXREG
021C
—
URX8
Receive Register
0000 0000 0000 0000
U2BRG
021E
Baud Rate Generator Prescaler
0000 0000 0000 0000
Legend:
u
= uninitialized bit; — = unimplemented bit, read as ‘0’
Note
1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.