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參數(shù)資料
| 型號： | DSP56F805FV80E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 71KB（35.5K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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56F805 Description
56F805 Technical Data, Rev. 16
Freescale Semiconductor
5
Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins
CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
Computer Operating Properly (COP) watchdog timer
Two dedicated external interrupt pins
External reset input pin for hardware reset
External reset output pin for system reset
JTAG/On-Chip Emulation (OnCE) module for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F805 Description
The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F805 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external
dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory (64K).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F805FV80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP144 3.6V |
| DSP56F805PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F805 16-Bit Hybrid Controller Product Brief |
| DSP56F807 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F807 16-bit Hybrid Processor |
| DSP56F807EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F807 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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