參數(shù)資料
型號： DSP56F805FV80
廠商： Freescale Semiconductor
文件頁數(shù)： 11/56頁
文件大?。?/td> 0K
描述： IC DSP 80MHZ 64KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝： 60
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 71KB（35.5K x 16）
程序存儲器類型： 閃存
RAM 容量： 2.5K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
JTAG/OnCE
56F805 Technical Data, Rev. 16
Freescale Semiconductor
19
2.14 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F805 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during
Table 2-18 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
(Schmitt)
Input, pulled
low internally
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
1
TMS
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
1
TDI
Input
(Schmitt)
Input, pulled
high internally
Test Data Input—This input pin provides a serial input data stream
to the JTAG/OnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
1
TRST
Input
(Schmitt)
Input, pulled
high internally
Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted at power-up and whenever RESET
is asserted. The only exception occurs in a debugging environment
when a hardware device reset is required and it is necessary not to
reset the OnCE/JTAG module. In this case, assert RESET, but do
not assert TRST.
Note:
For normal operation, connect TRST directly to VSS. If the design
is to be used in a debugging environment, TRST may be tied to VSS
through a 1K resistor.
1
DE
Output
Debug Event—DE provides a low pulse on recognized debug
events.
相關(guān)PDF資料
PDF描述
DSP56F803BU80 IC DSP 80MHZ 64KB FLASH 100LQFP
MC68332ACFC25 IC MCU 32BIT 25MHZ 132-PQFP
MC68332ACFC20 IC MCU 32BIT 20MHZ 132-PQFP
MCF5307FT66B IC MPU 32BIT COLDF 66MHZ 208FQFP
MCF5206FT25A IC MCU 32BIT COLDF 25MHZ 160-QFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F805FV80E 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F805FV80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSP56F805FV80E 制造商:Freescale Semiconductor 功能描述:DSP LQFP144 3.6V
DSP56F805PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F805 16-Bit Hybrid Controller Product Brief
DSP56F807 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F807 16-bit Hybrid Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*