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參數(shù)資料
| 型號： | DS90LV804TSQX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER/REPEATR LVDS 4CH 32LLP |
| 標準包裝： | 4,500 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVDS |
| 延遲時間： | 3.2ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 電流 - 電源： | 140mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-LLP-EP（5x5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | DS90LV804TSQX |
EN
OUT0+
OUT0-
IN0-
IN0+
OUT1+
OUT1-
IN1-
IN1+
OUT2+
OUT2-
IN2-
IN2+
OUT3+
OUT3-
IN3-
IN3+
SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013
DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater
Check for Samples: DS90LV804
In order to maximize signal integrity, the DS90LV804
1
FEATURES
features both an internal input and output (source)
23
800 Mbps Data Rate per Channel
termination to eliminate these extra components from
Low Output Skew and Jitter
the board, and to also place the terminations as close
as possible to receiver inputs and driver output. This
LVDS/CML/LVPECL Compatible Input, LVDS
is especially significant when driving longer cables.
Output
The DS90LV804, available in the WQFN (Leadless
On-Chip 100
Input and Output Termination
Leadframe
Package)
package,
minimizes
the
12 kV ESD Protection on LVDS Outputs
footprint, and improves system performance.
Single 3.3V Supply
An output enable pin is provided, which allows the
Very Low Power Consumption
user to place the LVDS outputs and internal biasing
Industrial -40 to +85°C Temperature Range
generators in a TRI-STATE, low power mode.
Small WQFN Package Footprint
The differential inputs interface to LVDS, and Bus
LVDS signals such as those on TI's 10-, 16-, and 18-
DESCRIPTION
bit Bus LVDS SerDes, as well as CML and LVPECL.
The DS90LV804 is a four channel 800 Mbps LVDS
The differential inputs are internally terminated with a
buffer/repeater. In many large systems, signals are
100
resistor to improve performance and minimize
distributed across cables and signal integrity is highly
board space. This function is especially useful for
dependent on the data rate, cable type, length, and
boosting signals over lossy cables or point-to-point
the termination scheme.
backplane configurations.
Block and Connection Diagrams
Figure 1. DS90LV804 Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
TRI-STATE is a registered trademark of National Semiconductor Corporation.
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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