參數(shù)資料
型號： DS89C21TMX
元件分類： 收發(fā)器
英文描述： Transceiver
中文描述： 收發(fā)器
文件頁數(shù)： 34/48頁
文件大?。?/td> 934K
代理商： DS89C21TMX
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
34 of 48
Table 11. Page Mode 2, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 11)
RD/WR
PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
MD2:MD0
STRETCH
CYCLES
4X/
CD0 = 100
2X
, CD1,
4X/
CD0 = 000
2X
, CD1,
4X/
CD0 = X10
2X
, CD1,
4X/
CD0 = X11
2X
, CD1,
000
0
0.5
1
2
2048
001
1
1
2
4
4096
010
2
2
4
8
8192
011
3
3
6
12
12,288
100
7
4
8
16
16,384
101
8
5
10
20
20,480
110
9
6
12
24
24,576
111
10
7
14
28
28,672
As shown in the previous tables, the stretch feature supports eight stretched external data-memory access options,
which can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on
external data memory access, and a MOVX instruction is completed in two basic memory cycles. When the stretch
value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles,
respectively. Note that the first stretch value does not result in adding four system clocks to the control signals. This
is because the first stretch uses one system clock to create additional address setup and data bus float time and
one system clock to create additional address and data hold time. When using very slow RAM and peripherals, a
larger stretch value (4–7) can be selected. In this stretch category, two stretch cycles are used to create additional
setup (the ALE pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to
create additional hold time. The following timing diagrams illustrate the external data memory access at divide-by-1
system clock mode (CD1:CD0 = 10b).
Figure 12
illustrates the external data-memory stretch-cycle timing relationship when PAGEE = 1 and
PAGES1:PAGES0 = 01. The stretch cycle shown is for a stretch value of 1 and is coincident with a page miss.
Note that the first stretch value does not result in adding four system clocks to the
RD
/
WR
control signals. This is
because the first stretch uses one system clock to create additional setup and one system clock to create
additional hold time.
Figure 13
shows the timing relationship for a slow peripheral interface (stretch value = 4). Note that a page hit data
memory cycle is shorter than a page miss data memory cycle. The ALE pulse width is also stretched by a stretch
cycle in the case of a page miss.
The stretched data memory bus cycle timing relationship for PAGES = 11 is identical to nonpage mode operation
since the basic data memory cycle always contains four system clocks in this page mode operation.
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