參數(shù)資料
型號： DS32512N
廠商： Maxim Integrated Products
文件頁數(shù)： 62/130頁
文件大?。?/td> 0K
描述： IC 12CH DS3/E3/STS1 LIU 484-BGA
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
類型： 線路接口裝置（LIU）
規(guī)程： DS3
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
供應商設備封裝： 484-BGA（23x23）
包裝： 托盤
DS32506/DS32508/DS32512
37 of 130
Table 8-9. Pseudorandom Pattern Generation
BERT.PCR REGISTER
PATTERN TYPE
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS
QRSS
TPIC,
RPIC
2
9-1 O.153 (511 type)
04
08
0
0xFFFF
0
2
11-1 O.152 and
O.153 (2047 type)
08
0A
0
0xFFFF
0
2
15-1 O.151
0D
0E
0
0xFFFF
1
2
20-1 O.153
10
13
0
0xFFFF
0
2
20-1 O.151 QRSS
02
13
0
1
0xFFFF
0
2
23-1 O.151
11
16
0
0xFFFF
1
Table 8-10. Repetitive Pattern Generation
BERT.PCR REGISTER
PATTERN TYPE
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS
QRSS
All 1s
NA
00
1
0
0xFFFF
All 0s
NA
00
1
0
0xFFFF
0xFFFE
Alternating 1s and 0s
NA
01
1
0
0xFFFF
0xFFFE
11001100...
NA
03
1
0
0xFFFF
0xFFFC
3 in 24
NA
17
1
0
0xFF20
0x0022
1 in 16
NA
0F
1
0
0xFFFF
0x0001
1 in 8
NA
07
1
0
0xFFFF
0xFF01
1 in 4
NA
03
1
0
0xFFFF
0xFFF1
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BERT.CR.TNPL for the pattern generator and BERT.CR.RNPL for the pattern detector. The BERT
must be enabled (PORT.CR3:BERTE = 1) before the pattern is loaded for the pattern load operation to take effect.
Monitoring the BERT requires reading the BERT.SR register, which contains the Bit-Error Count (BEC) bit and the
Out of Synchronization (OOS) bit. The BEC bit is set to one when the bit error counter is one or more. The OOS bit
is set to one when the pattern detector is not synchronized to the incoming pattern, which occurs when it receives 6
or more bit errors within a 64-bit window. The Receive BERT Bit Count Register (BERT.RBCR) and the Receive
BERT Bit Error-Count Register (BERT.RBECR) are updated upon the reception of a Performance Monitor Update
signal (e.g., BERT.CR.LPMU). This signal updates the registers with the bit and bit-error counts since the last
update and then resets the counters. See Section 8.7.4 for more details about performance monitor updates.
8.5.2 Receive Pattern Detection
The pattern detector synchronizes the receive pattern generator to the incoming pattern. The receive pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
n + xy + 1), the
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32 with y < n) in the BERT.PCR:PLF and PTF fields. The output of the
receive pattern generator is the feedback. If QRSS is enabled (BERT.PCR:QRSS = 1), the feedback is forced to be
an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. For PRBS and QRSS
patterns, the feedback is forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern
programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization.
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DS32512NA2 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube
DS32512NW 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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