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參數(shù)資料
| 型號： | DS32512+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 105/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | DS3 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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DS32506/DS32508/DS32512
76 of 130
Register Name:
LIU.SRL
Register Description:
LIU Status Register Latched
Register Address:
n * 80h + 2Ah
Bit #
15
14
13
12
11
10
9
8
Name
—
JAFL
JAEL
TDML
TFAILL
LOMCL
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
—
RGLCL
RPASL
RFAIL1L
RFAIL2L
RLOLL
ALOSL
Default
0
Bit 12: Jitter Attenuator Full Latched (JAFL).
This bit is set when the jitter attenuator buffer is full, or when data
has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAFIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 11: Jitter Attenuator Empty Latched (JAEL).
This bit is set when the jitter attenuator buffer is empty, or when
data has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAEIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 10: Transmit Driver Monitor Change Latched (TDML).
This bit is set when the LIU.SR:TDM bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TDMIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 9: Transmit Output Failure Change Latched (TFAILL).
This bit is set when the LIU.SR:TFAIL bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TFAILIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 8: Loss of Master Clock Latched (LOMCL).
This bit is set when the LIU.SR:LOMC bit is set. When set, this
bit causes an interrupt if interrupt enables LIU.SRIE:LOMCIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE
are all set.
Bit 5: Receive Gain Level Change Latched (RGLCL).
This bit is set when the receive gain level (LIU.RGLR:
RGL[7:0]) changes. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RGLCIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set.
Bit 4: Receive Preamp Status Change Latched (RPASL).
This bit is set when the LIU.SR:RPAS bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RPASIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 3: Receive Failure Type 1 Change Latched (RFAIL1L).
This bit is set when the LIU.SR:RFAIL1 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL1IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Receive Failure Type 2 Change Latched (RFAIL2L).
This bit is set when the LIU.SR:RFAIL2 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL2IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 1: Receive Loss of Lock Change Latched (RLOLL).
This bit is set when the LIU.SR:RLOL bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RLOLIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 0: Analog Loss of Signal Change Latched (ALOSL).
This bit is set when the LIU.SR:ALOS bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:ALOSIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32512+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512A2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS32512 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS32512N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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