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| 型號(hào)： | DS32508N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 66/130頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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8.5.3.1
Transmit Error Insertion
Errors can be inserted into the generated pattern one at a time or at a rate of one out of every 10
n bits. The value of
n is programmable (1 to 7 or off) in the BERT.TEICR:TEIR[2:0] configuration field. Single bit error insertion is
enabled by setting BERT.TEICR:BEI and can be initiated from the microprocessor interface or by the manual error
insertion pin (GPIOB2). See Section 8.7.5 for more information about manual error insertion.
8.6 Loopbacks
Each LIU has three internal loopbacks. See Figure 2-1. When only the hardware interface is enabled (IFSEL = 000
and HW = 1), loopbacks are controlled by the LBn[1:0] and LBS pins. When a microprocessor interface is enabled
≠ 000), loopbacks are controlled by the LB[1:0] and LBS fields in the PORT.CR3 register.
Analog loopback (ALB) connects the outgoing transmit signal back to the receiver’s analog front end. During ALB
Line loopback (LLB) connects the output of the receiver to the input of the transmitter. The LLB path does not
include the B3ZS/HDB3 decoder and encoder so that the signal looped back is exactly the same as the signal
received, including bipolar violations and code violations. During LLB, recovered clock and data are output on
Diagnostic loopback (DLB) connects the TCLK, TPOS/TDAT and TNEG pins to the RCLK, RPOS/RDAT, and
RNEG/RLCV pins. During DLB (with LLB disabled), the signal on TXP/TXN can be the normal transmit signal or an
AIS signal from the AIS generator. DLB and LLB can be enabled simultaneously to provide simultaneous remote
and local loopbacks.
8.7 Global Resources
8.7.1 Clock Rate Adapter (CLAD)
The CLAD is used to create multiple transmission-quality reference clocks from a single transmission-quality
(
±20ppm, low jitter) clock input on the REFCLK pin. The LIUs in the device need up to three different reference
clocks (DS3, E3, and STS-1) for use by the CDRs and jitter attenuators. Given one of these clock rates or any of
several other clock frequencies on the REFCLK pin, the CLAD can generate all three LIU reference clocks. The
internally generated reference clock signals can optionally be driven out on pins CLKA, CLKB, and CLKC for
external use. In addition a fourth frequency, either 77.76MHz or 19.44MHz, can be generated and driven out on the
CLKD pin for use in Telecom Bus applications.
When only the hardware interface is enabled (IFSEL = 000 and HW = 1), the CLAD is controlled by the CLADBYP
pin, and the REFCLK frequency is fixed at 19.44MHz. When the CLADBYP pin is high all PLLs in the CLAD are
bypassed and powered down, and the REFCLK pin is ignored. In this mode the CLKA, CLKB, and CLKC pins
become inputs, and the DS3, E3, and STS-1 reference clocks, respectively, are sourced from these pins.
Transmission-quality clocks (
±20ppm, low jitter) must be provided to these pins for each line rate required by the
LIUs. When CLADBYP is low, all four PLLs in the CLAD are enabled, and the generated DS3, E3, STS-1, and
When a microprocessor interface is enabled (IFSEL
≠ 000), the CLAD clock mode and the REFCLK frequency are
set by the GLOBAL.CR2:CLAD[6:4] bits, as shown in Table 8-11. When CLAD[6:4] = 000, all PLLs in the CLAD are
bypassed and powered down, and the REFCLK pin is ignored. In this mode the CLKA, CLKB, and CLKC pins
become inputs, and the DS3, E3, and STS-1 reference clocks, respectively, are sourced from these pins.
Transmission-quality clocks (
±20ppm, low jitter) must be provided to these pins for each line rate required by the
LIUs. CLAD[6:4] = 000 is equivalent to pulling the CLADBYP pin high. When CLAD[6:4]
≠ 000, the PLL circuits are
enabled as needed to generate the required clocks, as determined by the CLAD[6:0] bits and the LIU mode bits
(PORT.CR2:LM[1:0]). If a clock rate is not required as a reference clock, then the PLL used to generate that clock
is automatically disabled and powered down. The CLAD[3:0] bits are output enable controls for CLKA, CLKB,
CLKC and CLKD, respectively. Configuration bit GLOBAL.CR2:CLKD19 specifies the frequency to be output on the
CLKD pin (77.76MHz or 19.44MHz). Status register GLOBAL.SRL provides activity status for the REFCLK, CLKA,
Each LIU block indicates the absence of the reference clock it requires by setting its LIU.SR:LOMC bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32508N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32508N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32508NA2 | 制造商:Maxim Integrated Products 功能描述:DS32508NA2 X8 DS3/E3 LIU - Rail/Tube |
| DS32508N-W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32508-W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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