- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10993 > DS3170N+ (Maxim Integrated Products)IC TXRX DS3/E3 100-CSBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3170N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/230頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX DS3/E3 100-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 640 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | DS3，E3 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 120mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（11x11） |
| 包裝： | 托盤 |
| 包括： | DS3 調(diào)幀器，E3 調(diào)幀器，HDLC 控制器，芯片內(nèi) BERT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁
DS3170 DS3/E3 Single-Chip Transceiver
117 of 230
11 OVERALL REGISTER MAP
The register addresses of the global, test and the port are concatenated to cover the address range of 000 to 7FF.
The address map requires 9 bits of address, ADR[8:0].
The register banks that are not marked with an “X” are not writeable and read back all zeroes. Bits that are
underlined
Unused bits and registers marked with “—“ are ignored when written to, and return zero when read.
are read-only; all other bits are read-write.
Configuration registers can be written to and read from during a data path reset (
DRST low, and RST high).
However, all changes to these registers will be ignored during the data path reset. As a result, all initiating action
requiring a “0 to 1” transition must be re-initiated after the data path reset is released.
All counters saturate at their maximum count. A counter register is updated by asserting (low to high transition) the
performance monitoring update signal (PMU). During the counter register update process, the performance
monitoring status signal (PMS) will be deasserted. The counter register update process consists of loading the
counter register with the current count, resetting the counter, forcing the zero count status indication low for one
clock period, and then asserting PMS. No events shall be missed during an update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared. Once cleared, a latched
bit will not be set again until the associated event reoccurs (goes away and comes back). A latched on change bit
is a latched bit that is set when the event occurs, and when it goes away. A latched status bit can be cleared using
clear on read or clear on write techniques, selectable by the GL.CR1.LSBCRE bit. When clear on write is selected,
the latched bits in a latched status register will be cleared after the register is read from. If the device is configured
for 16-bit mode, all 16 latched status bits will be cleared. If the device is configured for 8-bit mode, only the 8 bits
being accessed will be cleared. When clear on write is selected, the latched bits in a latched status register will be
cleared when a logic 1 is written to that bit position. For example, writing a FFFFh to a 16-bit latched status register
will clear any latched status bit, whereas writing a 0001h will only clear latched bit 0 of the latched status register.
Reserved bits and registers are implemented in a different mode. Reserved configuration bits and registers can be
written and read, however they will not affect the operation of the current mode. Reserved status bits will be zero.
Reserved latched status bits cannot be set, however, they may remain set or get set during a mode change.
Reserved interrupt enable bits can be written and read, and can cause an interrupt if the associated latched status
bit is set. Reserved counter registers and the associated counter will retain the values held before a mode change,
however, the associated counter cannot be incremented. A performance monitor update will operate normally. If
the data path reset is set during or after a mode change, the latched status bits and counter registers (with the
associated counters) will be automatically cleared. If the data path reset is not used, then the latched status bits
must be cleared via the register interface in the normal manner. And, the counter registers must be cleared by
performing two performance monitor updates. The first to clear the associated counter, and load the current count
into the counter register, and the second to clear the counter register.
The term “global” is used to make the register names compatible with the mult-port versions (DS3174, DS3173,
DS3172, DS3171) of this device.
NOTE: The
RDY signal will not go active if the user attempts to read or write unused registers not assigned to any
design blocks. The
RDY signal will go active if the user writes or reads reserved registers or unused registers within
design blocks.
Table 11-1. Register Address Map
Address
offset
Description
000 - 01F
Global registers
020 – 03F
Unused
040 - 05F
Port control registers
060 – 07F
BERT
080 – 08B
Unused
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2151QB | IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS21Q58LN+ | IC TXRX E1 QUAD 3.3V 100LQFP |
| DS26504LN+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS21352G | IC TXRX T1 1-CHIP 3.3V 100-BGA |
| DS2174QN+T&R | IC BERT ENHANCED 44-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3170N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3170N+T&R | 制造商:Maxim Integrated Products 功能描述:SINGLE PORT DS3/E3 SCT T&R IND LF - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TXRX DS3/E3 100CSBGA |
| DS3170N+T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3171 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3171N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。